%
% Filename:    ml605_fmc150_postgeneration.m
%
% Description: Defines board-specific parameters (e.g. ucf file, 
%              non-memory mapped ports) before invoking the 
%              generic JTAG post-generation callback function.

function st = ml605_fmc150_postgeneration(params)

  % The system clock is differential.
  params.('is_differential_clock') = 'true';

  % Device position in the boundary scan chain (beginning at 1).
  params.('boundary_scan_position') = '2';

  % Instruction register length of every scan chain device. 
  params.('instruction_register_lengths') = '[8, 10]';

  % Constraints file to use for this compilation target.
  params.('ucf_template') = 'ml605_fmc150.ucf'; 

  % Define non-memory mapped ports.
  non_mm_ports.('CPU_RESET') = {'in', 1};
  non_mm_ports.('GPIO_DIP_SW') = {'in', 8};
  non_mm_ports.('GPIO_SW_C') = {'in', 1};
  non_mm_ports.('GPIO_SW_E') = {'in', 1};
  non_mm_ports.('GPIO_SW_N') = {'in', 1};
  non_mm_ports.('GPIO_SW_S') = {'in', 1};
  non_mm_ports.('GPIO_SW_W') = {'in', 1};
  non_mm_ports.('CLK_AB_N') = {'in', 1};
  non_mm_ports.('CLK_AB_P') = {'in', 1};
  non_mm_ports.('CHA_N') = {'in', 7};
  non_mm_ports.('CHA_P') = {'in', 7};
  non_mm_ports.('CHB_N') = {'in', 7};
  non_mm_ports.('CHB_P') = {'in', 7};
  non_mm_ports.('CLK_TO_FPGA_N') = {'in', 1};
  non_mm_ports.('CLK_TO_FPGA_P') = {'in', 1};
  non_mm_ports.('EXT_TRIGGER_N') = {'in', 1};
  non_mm_ports.('EXT_TRIGGER_P') = {'in', 1};
  non_mm_ports.('ADC_SDO') = {'in', 1};
  non_mm_ports.('CDCE_SDO') = {'in', 1};
  non_mm_ports.('PLL_STATUS') = {'in', 1};
  non_mm_ports.('DAC_SDO') = {'in', 1};
  non_mm_ports.('MON_SDO') = {'in', 1};
  non_mm_ports.('MON_N_INT') = {'in', 1};
  non_mm_ports.('PRSNT_M2C_L') = {'in', 1};
  non_mm_ports.('GPIO_LED') = {'out', 8};
  non_mm_ports.('GPIO_LED_C') = {'out', 1};
  non_mm_ports.('GPIO_LED_E') = {'out', 1};
  non_mm_ports.('GPIO_LED_N') = {'out', 1};
  non_mm_ports.('GPIO_LED_S') = {'out', 1};
  non_mm_ports.('GPIO_LED_W') = {'out', 1};
  non_mm_ports.('DAC_DCLK_N') = {'out', 1};
  non_mm_ports.('DAC_DCLK_P') = {'out', 1};
  non_mm_ports.('DAC_DATA_N') = {'out', 8};
  non_mm_ports.('DAC_DATA_P') = {'out', 8};
  non_mm_ports.('DAC_FRAME_N') = {'out', 1};
  non_mm_ports.('DAC_FRAME_P') = {'out', 1};
  non_mm_ports.('TXENABLE') = {'out', 1};
  non_mm_ports.('SPI_SCLK') = {'out', 1};
  non_mm_ports.('SPI_SDATA') = {'out', 1};
  non_mm_ports.('ADC_N_EN') = {'out', 1};
  non_mm_ports.('ADC_RESET') = {'out', 1};
  non_mm_ports.('CDCE_N_EN') = {'out', 1};
  non_mm_ports.('CDCE_N_RESET') = {'out', 1};
  non_mm_ports.('CDCE_N_PD') = {'out', 1};
  non_mm_ports.('REF_EN') = {'out', 1};
  non_mm_ports.('DAC_N_EN') = {'out', 1};
  non_mm_ports.('MON_N_EN') = {'out', 1};
  non_mm_ports.('MON_N_RESET') = {'out', 1};
  params.('non_memory_mapped_ports') = non_mm_ports;

  % You may use your own top-level netlist file by uncommenting the 
  % following line and setting the 'vendor_toplevel' field accordingly.
  % params.('vendor_toplevel') = 'ml605_fmc150_toplevel';

  % If you use your own top-level, you must tell SysGen what netlist 
  % files are required.  Set the 'vendor_netlists' field to a cell 
  % array listing the required file names. 
  % params.('vendor_netlists') = {'ml605_fmc150_toplevel.ngc','ml605_fmc150.edf'};

  % Invoke the JTAG post-generation callback function to run
  % Xilinx tools and create a run-time co-simulation token.
  try
    st = xlJTAGPostGeneration(params);
  catch
    errordlg(['-- An unknown error was encountered while running ' ...
             'the JTAG hardware co-simulation flow for the ' ...
             'ML605_FMC150']);
    st = 1;
  end
